Recently operation processing of a central processing unit (CPU) is speeded up and hence its operation speed is much faster than those of peripheral circuits. When the CPU reads out data stored in a register of low speed, latency increases and processing efficiency is lowered. To prevent the processing efficiency from being lowered, JP 2009-289232A (FIG. 1) for example discloses a configuration, in which data stored in peripheral modules (low speed registers) are copied into a register entry (high speed register), and CPUs acquire the data by accessing only the register entry.
To maintain coherency between the peripheral modules and the register entry, data of same value are written in both modules and the register entry. In the midst of write cycle of a peripheral bus of low speed, a write completion notification is transmitted to the register entry and a flag indicating agreement of data (parity bit) is set. The CPUs check, by checking a logic level of the parity bit, whether the data are the same between the peripheral modules and the register entry.
In a microcomputer connected to a communication network, a CPU performs access to a peripheral circuit within a chip at high speeds but performs communications through a communication interface and a network at low speeds. In case that the above-described technology is directly applied to such a microcomputer, it is necessary to provide a high speed register between the CPU and a communication interface (buffer) and connect the communication interface and the high speed register by an exclusive bus, which is capable of high speed data transfer. However it is not readily possible because of difficulty in adapting the communication interface to be operable at high access speed and of high cost.